Webhdlin_report_inferred_modules If this flag is set to true, Design Compiler generates a report about inferred latches, flip-flops, and three-state and multiplexer devices. Redirect the report file by entering: dc_shell> elaborate –f vhdl > my_file.report hdlin_resource_allocation When the flag is set to constraint_driven, this flag en- WebIn Synopsys one can write: (VHDL code here will be synthesized) --pragma translate_off. (all VHDL code here is ignored) --pragma translate_on. (VHDL code here will be again synthesized) And this must be in setup-script: hdlin_translate_off_skip_text = true. However, I have a question too: does anyone know how to include some VHDL.
HDL Compiler Directives 9 - Huihoo
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SMU
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